| TDR v2.0 | ● LIVE
CLK: 72MHz PW: 0.52μs CNN: 97.3% SLIDE: 01/14

CABLESCOPE

AI-Enhanced Time Domain Reflectometer
Advanced Cable Fault Classification & Localization
using Hybrid CNNs and Equivalent-Time Sampling
DOMAIN Electronics & Telecom Engineering
SPEC AI / ML / Deep Learning
CableScope Prototype
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ABSTRACT

Traditional Time Domain Reflectometers (TDRs) are prohibitively expensive and require highly skilled technicians to manually interpret complex waveform reflections.

CableScope is a low-cost, AI-driven TDR system designed to automatically detect, classify, and pinpoint faults in communication cables (Cat5e, Cat6, Coaxial).

By combining a custom analog front-end utilizing a DAC-driven comparator sweep for sub-nanosecond Equivalent-Time Sampling (ETS) with a Hybrid CNN (1D-CNN + 2D-CNN Wavelets), CableScope achieves commercial-grade (≈ 10 cm) spatial resolution.

The system features a fully integrated Python/FastAPI backend and a Next.js/React frontend, providing an intuitive, real-time diagnostic dashboard.

KEY METRICS
Resolution~10 cm
Sampling~1 ns ETS
AI ModelHybrid CNN
Cost₹1,600
CablesCat5e/6, Coax
BackendFastAPI/Python
FrontendNext.js/React
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PROBLEM STATEMENT

HIGH COST

Industry-grade TDRs with 10 cm resolution rely on expensive FPGAs, proprietary DSPs, and avalanche transistors — costing upwards of ₹3,00,000. Inaccessible for small IT teams and educational labs.

HW BOTTLENECK

Standard microcontrollers (72 MHz STM32) cannot sample fast enough for short cables. Baseline ADC resolution limits spatial accuracy to ≈ 1.4 meters.

👁
MANUAL INTERPRET.

Identifying whether a waveform spike represents an Open, Short, or impedance noise requires specialized training and is prone to human error in noisy environments.

THE NEED

A cost-effective, intelligent system that replaces expensive hardware delay lines with smart analog sweeping, and manual analysis with automated AI classification.

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DOMAIN

CORE DOMAIN
Electronics & Telecommunication Engineering
EXTC
SPECIALIZATION
Artificial Intelligence & Machine Learning
Deep Learning / Signal Processing
TDR Equivalent-Time Sampling Hybrid CNN Fault Classification Impedance Mismatch Waveform Analysis STM32 PyTorch FastAPI Real-Time Systems
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LITERATURE SURVEY

01
Principles of TDR

Fast rise-time pulse reflects at impedance mismatches. The Reflection Coefficient defines fault type:

Γ = (ZL − Z0) / (ZL + Z0)
02
Equivalent-Time Sampling

Technique from high-end oscilloscopes: reconstructs repetitive high-speed signals by sequentially delaying the ADC trigger, bypassing Nyquist limits.

03
Deep Learning for Time-Series

Hybrid CNNs (1D-CNN + 2D-CNN with wavelet transforms) excel at extracting spatial and temporal features, outperforming classical gradient thresholding methods.

04
NASA Wire Evaluation

TDR is primary technique for detecting chafed cables in spacecraft. NASA's Kennedy Space Center developed In Situ Wire Damage Detection System.

05
FDTD Cable Modeling

NASA Technical Reports use Finite-Difference Time-Domain methods to predict TDR signatures, validating simulated synthetic data approaches.

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METHODOLOGY

PHASE 1 HARDWARE FRONT-END
STM32F303RE generates 3.3V trigger pulse
Voltage-Controlled Delay Line: LM319 comparator + RC ramp (100pF, 3.3kΩ)
DAC sweep achieves ≈ 1ns sampling resolution
74AC14 Hex Inverter sharpens to <2ns fast edge
Impedance-matched 200Ω trimpot prevents source reflections
PHASE 2 SIGNAL PROCESSING
ADC captures 1024-sample waveform → serial → FastAPI backend
Synthetic data engine (simulator.py) for AI training
Attenuation modeling: e−αD
Gaussian white noise injection for robustness
PHASE 3 AI & VISUALIZATION
Hybrid CNN model classifies fault type (Open / Short)
Distance extraction from temporal features
Next.js/React dashboard with Tailwind CSS
Live waveform via recharts + confidence score
Cable Fault ADC Return FastAPI Backend Hybrid CNN Classification React UI
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SYSTEM MODEL

1RC Timing Ramp
2Delay Slicer (LM319)
3Pulse Driver (74AC14)
4Cable Interface (BNC/RJ45)
5ADC Return + Protection
ANALOG FRONT-END

DAC-driven comparator sweep generates a programmable delay. An RC ramp (100pF, 3.3kΩ) is compared against the DAC voltage by an LM319, producing a delayed trigger that shifts the ADC sampling window by ≈1ns per step.

PULSE GENERATION

The 74AC14 hex inverter chain sharpens the delayed trigger into a fast-edge (<2ns rise time) 3.3V pulse. A 200Ω trimpot provides impedance matching at the cable launch point to minimize source reflections.

SIGNAL CAPTURE

Reflected waveform is captured by the STM32's 12-bit ADC with BAT54S clamping protection. 1024 ETS samples are assembled into a composite waveform and streamed to the backend via UART/USB.

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SYSTEM ARCHITECTURE

SYSTEM ARCHITECTURE — BLOCK DIAGRAM
System Architecture
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CIRCUIT SCHEMATICS

CABLESCOPE V2.0 — FULL CIRCUIT SCHEMATIC
Circuit Schematic
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3D PCB MODEL

CABLESCOPE V2.0 — TE DESIGN FORM FACTOR
3D PCB Model
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COMPONENTS

COMPUTE / HOST
STM32F303RE Nucleo-64 Development Board
Host Laptop (Ryzen 5 5600H / RTX 3050)
LOGIC & TIMING
MC74AC14DR2G Hex Inverter (SOIC-14)
LM319DT High-Speed Comparator (SOIC-14)
PASSIVES
Bourns 200Ω Trimpot
BAT54S Schottky Diode
3.3kΩ Resistor, 100pF Ceramic Capacitor
CONNECTIVITY
BNC Female PCB Mount (50Ω) — Coaxial
RJ45 Female Breakout — Ethernet
PCB
Custom 2-Layer High-Speed PCB with unbroken ground plane
PCB V2.0
CABLESCOPE V2.0 PCB
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APPLICATIONS

IT INFRASTRUCTURE

Rapid troubleshooting of Cat5e/Cat6 Ethernet runs in server rooms and office networks.

AEROSPACE & AVIONICS

Identifying intermittent faults, chafing, and opens in aircraft or spacecraft wiring harnesses. Aligned with NASA TDR goals.

TELECOM

Detecting breaks or shorts in long underground or aerial coaxial cable runs.

MANUFACTURING QC

Automated end-of-line testing for cable spools — zero defects before shipping.

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BILL OF COMPONENTS

Cost Estimation for Custom V2.0 PCB — Excluding STM32F303RE and Host Compute
COMPONENT COST (₹)
MC74AC14DR2G Hex Inverter 30
LM319DT High-Speed Comparator 32
BNC Connector Female (RA PCB Mount) 296
RJ45 Female PCB Mount 14
Bourns 200Ω Trimpot & BAT54S Diode 48
RC Ramp Passives & Headers 15
Custom 2-Layer PCB Fabrication ≈ 1,165
TOTAL ESTIMATED HARDWARE ≈ ₹1,600
VS INDUSTRY TDR
₹3,00,000+
₹1,600
187× CHEAPER
PCB Mounted
NUCLEO HAT FORM FACTOR
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REFERENCES

[1] "A Simple and Efficient Computational Approach to Chafed Cable Time-Domain Reflectometry Signature Prediction" — NASA Technical Reports Server (NTRS), Doc ID: 20090035829.
[2] "In Situ Wire Damage Detection and Rerouting System" — NASA Technology Transfer Program, Kennedy Space Center (KSC-TOPS-6).
[3] "A PC Based Time Domain Reflectometer for Space Station Cable Fault Isolation" — NASA Johnson Space Center, NTRS Doc ID: 19960022613.
[4] "Shielded-Twisted-Pair Cable Model for Chafe Fault Detection via Time-Domain Reflectometry" — NASA Ames Research Center, TM-2012-216001.
[5] Datasheets: STMicroelectronics STM32F303RE, ONSEMI 74AC14, STMicroelectronics LM319.
[6] "Deep Learning for Time Series Classification: A Review" — IEEE Access.
[7] React/Next.js and FastAPI official documentation for asynchronous web architecture.